The present invention relates to a system for repairing a semiconductor memory device having a spare memory section in a form such as spare lines or spare blocks, wherein a line including a defective bit or bits is replaced with, for example, a spare line so that the device is placed in acceptable form.
Generally, programmable read-only memory arrays (PROMs) and random access memory arrays (RAMs) have an addressable binary array formed in a matrix of rows and columns and a decoder associated with the array. As it is known in the art, such memory devices are provided therein with spare word lines and data lines arranged in rows and columns (these lines will be termed generically spare lines when referred to inclusively) so that a line including a defective bit or bits is replaced with a spare line, and this arrangement is significantly contributes to the enhancement of the yield in manufacturing semiconductor memory devices.
One technical problem with such memory devices with spare lines is to determine which ones of the spare lines on rows and/or columns should be used for relieving a plurality of defective bits existing at random in the array.
Prior art processes for relieving defective bits through the selective use of spare lines are described in an article entitled, "Laser Programmable Redundancy and Yield improvement in 64K DRAM", by Robert T. Smith et al., IEEE Journal of Solid-state Circuits, Vol. SC-16, No. 5, October 1981, and an article entitled, "Testing System for Redundant Memory", by Y. Hayasaka et al., IEEE Test Conference 1982.
In introducing spare lines or blocks in a semiconductor memory device, the consideration on the device structure and physical structure of the memory device becomes important, and this is also true in the analysis for repairing a semiconductor memory device. Namely, it is desirable from the viewpoint of device structure and physical structure of the memory device to choose the best solution out of a plurality of possible solutions for repair.
A recent trend of semiconductor memory devices is the provision of spare blocks which allow simultaneous replacement of a number of lines in an area in which defective bits exist. Spare blocks are provided with an associated programmable decoder on which the address of block including defective bits is programmed. Spare blocks may include row-directional blocks and column-directional blocks, and it is necessary to determine which spare block should be used first on the basis of the quality and performance considerations for the device when the marginal operating conditions differ due to the disposition of spare blocks in the device.
The decoder is programmed either through the electrical process as disclosed in, for example, Japanese Patent Laid-open No. 53-10228 (U.S. patent application Ser. No. 705,997), or by using the laser beam. These programming methods, however, render stress to the semiconductor memory device, resulting possibly in the deterioration of reliability. Provided that the programmable decoder is written in only for logical 1's bits and the number of 1's bits depends on the address of a block including defective bits, the solution for repair with the least number of 1's bits is desirable. The determination of a solution for repair in consideration of retaining the device quality, performance and reliability is not taken into account in the above-mentioned two methods.